题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);
//*************code***********//
    parameter S0 = 4'd0001;
    parameter S1 = 4'd0010;
    parameter S2 = 4'd0100;
    parameter S3 = 4'd1000;

    reg [3:0] c_state;
    reg [3:0] n_state;
    
    always @(posedge clk or negedge rst) begin
        if(!rst)
            c_state <= S0;
        else
            c_state <= n_state;
    end
    
    always @(*) begin
        case(c_state)
            S0: if(data == 1) n_state <= S1;else n_state <= c_state;
            S1: if(data == 1) n_state <= S2;else n_state <= c_state;
            S2: if(data == 1) n_state <= S3;else n_state <= c_state;
            S3: if(data == 1) n_state <= S0;else n_state <= c_state;
            default: n_state <= S1;
        endcase
    end
    
    always @(posedge clk or negedge rst) begin
        if(!rst)
            flag <= 1'b0;
        else begin
            case(c_state)
                S3:if(data) flag <= 1'b1;else flag <= 1'b0;
                default: flag <= 1'b0;
            endcase
        end
    end
    
//*************code***********//
endmodule