题解 | #使用函数实现数据大小端转换#

搞不懂为啥非要加上clk，rst信号,咱也不懂咱也不敢问

````timescale 1ns/1ns
module function_mod(
    input clk,
    input rst_n,
    
	input [3:0]a,
	input [3:0]b,
	
	output [3:0]c,
	output [3:0]d
);
    assign c = rst_n?revrs(a):0;
    assign d = rst_n?revrs(b):0;
 
    function [3:0] revrs;
        input [3:0] datain;
        integer i;
            for (i=0;i<4;i=i+1)
                begin :reverse
                    revrs[i] = datain[3-i];
                end
    endfunction

endmodule