题解 | 异步复位同步释放

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
reg rst_n_dly;
reg rst_n_dly_syn;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        rst_n_dly <= 1'b0;
    else
        rst_n_dly <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        rst_n_dly_syn <= 1'b0;
    else
        rst_n_dly_syn <= rst_n_dly;
end

always@(posedge clk or negedge rst_n_dly_syn)
begin
    if(!rst_n_dly_syn)
        dout <= 1'b0;
    else
        dout <= d;
end

//*************code***********//
endmodule