题解 | 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//

reg [15:0] reg_d;
reg [4:0]  reg_out;

assign out = reg_out;
assign validout = sel?1:0;

always@(posedge clk or negedge rst)begin
    if(!rst)
    reg_d<=0;
    else if(sel == 0)
    reg_d<=d;
end

always@(posedge clk or negedge rst)begin
    if(!rst)
    reg_out<=0;
    else if(sel == 0)
    reg_out<=0;
    else if(sel == 1)
    reg_out<=reg_d[3:0]+reg_d[7:4];
    else if(sel == 2)
    reg_out<=reg_d[3:0]+reg_d[11:8];
    else if(sel == 3)
    reg_out<=reg_d[3:0]+reg_d[15:12];
end


//*************code***********//
endmodule