题解 | 根据状态转移写状态机-二段式

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b100;
parameter S4 = 3'b110;
reg [2:0] state;
reg [2:0] nextstate;
//两段式状态机
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		state <= S0;
	end
	else begin
		state <= nextstate;
	end
end

always@(*)begin
	case(state)
	S0: begin
		flag = 1'b0;
		nextstate = data? S1:S0;
	end
	S1: begin
		flag = 1'b0;
		nextstate = data? S2:S1;
	end
	S2: begin
		flag = 1'b0;
		nextstate = data? S3:S2;
	end
	S3: begin
		flag = 1'b0;
		nextstate = data? S4:S3;
	end
	S4: begin
		flag = 1'b1;
		nextstate = data? S1:S0;
	end
	endcase
end

endmodule