题解 | 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
//ready_a一直拉高
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		ready_a <= 1'b0;
	end
	else
	begin
		ready_a <= 1'b1;
	end
end

//计6个数的计数器
reg [3:0] cnt;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		cnt <= 4'b0;
		data_b_tmp <= 6'b0;
	end
	else 
	if(valid_a && cnt != 4'd5)
	begin
		cnt <= cnt + 1;
	end
	else 
	if(valid_a && cnt == 4'd5)
	begin
		cnt <= 4'b0;
	end
	else 
	begin
		cnt <= cnt;
	end
end

reg [5:0] data_b_tmp;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		data_b_tmp <= 6'b0;
	end
	else
	if(valid_a && ready_a)
	begin
		data_b_tmp <= {data_a,data_b_tmp[5:1]};
	end
end


//valid_b:当计数到5时候拉高
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		valid_b <= 1'b0;
		data_b <= 6'b0;
	end
	else
	if(cnt == 4'd5)
	begin
		valid_b <= 1'b1;
		 data_b <= {data_a, data_b_tmp[5:1]};//此句要注意
	end
	else
	begin
		valid_b <= 1'b0;
	end
end




endmodule