题解 | 信号发生器

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);

//方波的周期是20，锯齿波的周期是21，三角波的周期是40  
reg [5:0] count;    //矩形脉冲使用
reg flag;   //三角脉冲使用，高为上升，低为下降
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		wave <= 5'd0;
		count <= 5'd0;
		flag <= 1'b0;
	end
	else
	begin
		case(wave_choise)
		2'b00:
		begin
			if(count == 5'd9)
			begin
				wave <= 5'd20;
				count <= count + 1;
			end
			else
			if(count == 5'd19)
			begin
				wave <= 5'd0;
				count <= 5'd0;
			end
			else
			begin
				wave <= wave;
				count <= count + 1;
			end
		end
		2'b01:
		begin
			if(wave == 5'd20)
			begin
				wave <= 5'd0;
			end
			else
			begin
				wave <= wave + 1;
			end
		end
		2'b10:
		begin
			if(flag)//当是上升时候
			begin
				if(wave < 5'd20)
				begin
					flag <= flag;
					wave <= wave + 1;
				end
				else
				if(wave == 5'd20)
				begin
					flag <= ~flag;
					wave <= wave - 1;
				end
			end
			else//当是下降时候
			begin
				if(wave > 5'd0)
				begin
					flag <= flag;
					wave <= wave - 1;
				end
				else
				if(wave == 5'd0)
				begin
					flag <= ~flag;
					wave <= wave + 1;
				end
			end
		end
		default:
			wave <= 5'd0;
		endcase
	end
end

endmodule