题解 | 含有无关项的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0] a_temp;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
	a_temp <= 1'b0;
end
else 
begin
	a_temp <= {a_temp[7:0],a};
end

always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
	match <= 1'b0;
end
else 
if(a_temp[8:6]==3'b011 && a_temp[2:0]==3'b110)
begin
	match <= 1'b1;
end
else
begin
	match <= 1'b0;	
end


endmodule