题解 | 实现3-8译码器①

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output reg       Y0_n   ,  
   output reg       Y1_n   , 
   output reg       Y2_n   , 
   output reg       Y3_n   , 
   output reg       Y4_n   , 
   output reg       Y5_n   , 
   output reg       Y6_n   , 
   output reg       Y7_n   
);




always@(*)begin
    if(!E3 | E2_n | E1_n)begin
        Y0_n = 1;
        Y1_n = 1;
        Y2_n = 1;
        Y3_n = 1;
        Y4_n = 1;
        Y5_n = 1;
        Y6_n = 1;
        Y7_n = 1;
    end
    else begin
        Y0_n = ~(~A2&~A1&~A0);
        Y1_n = ~(~A2&~A1&A0);
        Y2_n = ~(~A2&A1&~A0);
        Y3_n = ~(~A2&A1&A0);
        Y4_n = ~(A2&~A1&~A0);
        Y5_n = ~(A2&~A1&A0);
        Y6_n = ~(A2&A1&~A0);
        Y7_n = ~(A2&A1&A0);
    end
 
end
endmodule