题解 | 根据状态转移写状态机-三段式

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//从图中可以看出是mealy机
reg [1:0] current_state,next_state;
parameter S0=2'd0,S1=2'd1,S2=2'd2,S3=2'd3;

always@(posedge clk or negedge rst)
  if(!rst)
    current_state <= S0;
  else
    current_state <= next_state;

always@(*)
  case(current_state)
  S0: next_state = data ? S1 : S0;
  S1: next_state = data ? S2 : S1;
  S2: next_state = data ? S3 : S2;
  S3: next_state = data ? S0 : S3;
  default: next_state = S0;
  endcase

always@(posedge clk or negedge rst)
  if(!rst)
    flag <= 1'b0;
  else if(current_state == S3 && data == 1'b1)
    flag <= 1'b1;
  else
    flag <= 1'b0;


//*************code***********//
endmodule