题解 | 根据状态转移图实现时序电路

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

    reg [1:0] state;
    reg [1:0] next_state;
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
    // State transition logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            state <= S0; // Reset to initial state
        else
            state <= next_state; // Transition to next state
    end
    // Next state logic
    always @(*) begin
        case (state)
            S0: next_state = C ? S1 : S0; 
            S1: next_state = C ? S1 : S3;
            S2: next_state = C ? S2 : S0;
            S3: next_state = C ? S2 : S3;
            default: next_state = S0; // Default case
        endcase
    end
    // Output logic
    assign Y = ((state == S3) || (state == S2 && next_state == S2)) ? 1'b1 : 1'b0; // Output is high when in state S2
endmodule