题解 | 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] d_reg;
always@(posedge clk or negedge rst)
if(!rst) begin
  d_reg <= 0;
  validout  <= 0;
  out <= 0;
end
else begin
    case(sel)
    0: begin
        d_reg <= d;
        validout <= 0;
        out <= 0;
    end
    1: begin
        d_reg <= d_reg;
        validout <= 1;
        out <= d_reg[3:0]+d_reg[7:4];
    end
    2: begin
        d_reg <= d_reg;
        validout <= 1;
        out <= d_reg [3:0] + d_reg[11:8];
    end
    3: begin
        d_reg <= d_reg;
        validout <= 1;
        out <= d_reg[3:0] + d_reg[15:12];
    end
    endcase
end

//*************code***********//
endmodule