题解 | 格雷码计数器

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
// reg [3:0] cnt_bin;
// always@(posedge clk or negedge rst_n)
// if(!rst_n)
//   cnt_bin <= 0;
// else
//   cnt_bin <= cnt_bin + 1;


// always@(posedge clk or negedge rst_n)
// if(!rst_n)
//   gray_out <= 0;
// else 
//   gray_out <= (cnt_bin >> 1) ^ cnt_bin;
//不知道为什么上面的答案不对，看了一下答案给的波形图，发现是两个周期才变化一次
reg flag;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  flag <= 0;
else 
  flag <= ~flag;

reg [3:0] cnt_bin;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  cnt_bin <= 0;
else
  cnt_bin <= (!flag) ? (cnt_bin + 1): cnt_bin;


always@(posedge clk or negedge rst_n)
if(!rst_n)
  gray_out <= 0;
else 
  gray_out <= (cnt_bin >> 1) ^ cnt_bin;
endmodule