题解 | 输入序列连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [7:0] reg_a;//寄存器

always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	reg_a <= 8'b0000_0000;
	end
else begin
	reg_a <= {reg_a[6:0],a};//使用移位操作，新输入数据在低位，所以进行左移操作
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	match <= 1'b0;
	end
else if(reg_a == 8'b0111_0001)begin
	match <= 1'b1;
end
else begin
	match <= 1'b0;
end
end

 
endmodule