题解 | 边沿检测

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
reg reg_a;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	reg_a <= 1'b0;
end
else begin
	reg_a <= a;	
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	rise <= 0;
	down <= 0;
	reg_a <= a;
end
else if((reg_a==1'b0)&&(a==1'b1))begin
		rise <= 1'b1;down <= 1'b0;
end
else if((reg_a==1'b1)&&(a==1'b0))begin
		rise <= 1'b0;down <= 1'b1;
end
else begin 
rise <= 1'b0;
down <= 1'b0;
end
end
endmodule