题解 | 格雷码计数器

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    reg  clk2;
    reg [3:0] counter;
    reg [3:0] gray_out_d;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)clk2<='d0;
        else
            clk2<=~clk2;
    end

    always@(posedge clk2 or negedge rst_n)begin
        if(!rst_n)counter<='d0;
        else
            counter <= counter + 1'b1;
    end

    always@(*)begin
        if(!rst_n)gray_out_d<='d0;
        else
        gray_out_d = counter^(counter>>1);
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)gray_out<='d0;
        else
            gray_out <= gray_out_d;
    end
endmodule

照着时序图修改直至通过。。