题解 | 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] d_reg;
always@(posedge clk or negedge rst)begin //复位下降沿还是上升沿
    if(rst == 0)begin
        out <= 5'd0;
        validout <= 1'b0;
        d_reg <= 16'd0;
    end
    else begin
        case(sel)
            0: begin
                out <= 5'd0;
                validout <= 1'b0;
                d_reg <= d;
            end
            1: begin
                out <= d_reg[3:0] + d_reg[7:4];
                validout <= 1'b1;
            end
            2: begin
                out <= d_reg[3:0] + d_reg[11:8];
                validout <= 1'b1;
            end
            3: begin
                out <= d_reg[3:0] + d_reg[15:12];
                validout <= 1'b1;
            end
            default : begin
                out <= 5'd0;
                validout <= 1'b0;
            end
        endcase
    end
end

//*************code***********//
endmodule