题解 | 优先编码器电路①
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); always@(*) begin Y_n[3] = I_n[7] & I_n[8]; Y_n[2] = ~I_n[8] | (I_n[8] & (I_n[6] & I_n[5] & I_n[4] & I_n[3])); Y_n[1] = ~I_n[8] | (I_n[8] & (I_n[6] & I_n[5] & I_n[2] & I_n[1])); Y_n[0] = I_n[8] & (I_n[6] & I_n[4] & I_n[2] & I_n[0]); end endmodule
硬刚/卡洛图~