题解 | 使用子模块实现三输入数的大小比较
`timescale 1ns/1ns module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c, output [7:0]d ); wire [7:0] d1,d2; compare compare1(clk,rst_n,a,b,d1); compare compare2(clk,rst_n,a,c,d2); compare compare3(clk,rst_n,d1,d2,d); endmodule module compare ( input clk,rst_n, input [7:0] a,b, output reg [7:0] c ); always @(posedge clk or negedge rst_n) begin if(!rst_n) begin c <= 0; end else begin c <= (a<b)?a:b; end end endmodule
`timescale 1ns/1ns module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c, output [7:0]d ); reg [7:0] de1,de2; wire [7:0] d1,d2; always @(posedge clk or negedge rst_n) begin if(!rst_n) begin de1 <= 0; de2 <= 0; end else begin de1 <= d2; de2 <= de1; end end compare compare1(a,b,d1); compare compare2(c,d1,d2); assign d = de2; endmodule module compare ( input [7:0] a,b, output [7:0] c ); assign c = (a<b)?a:b; endmodule
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