题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
reg [1:0] cnt;
reg valid_in_temp;
reg [3:0] din;
always@(posedge clk or negedge rst)begin
	if(!rst)
		cnt <= 2'd0;
	else
	    cnt <= cnt + 1'b1;
end
always@(posedge clk or negedge rst)begin
	if(!rst)
		valid_in_temp <= 1'b0;
	else
		valid_in_temp <= (cnt == 3) ? 1'b1 : 1'b0;
end
assign valid_in = valid_in_temp;

always@(posedge clk or negedge rst)begin
	if(!rst)
		din <= 3'd0;
	else begin
		if (cnt == 3)
			din <= d;
		else
			din <= {din[2:0],din[3]};
	end    
end
assign dout = din[3];
//*************code***********//

endmodule