题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
logic [1:0] cnt;
always @(posedge clk or negedge rst) begin
  if(!rst) begin
	cnt <= 'd0;
  end
  else begin
	cnt <= cnt +'d1;
  end
end

logic valid;
always @(posedge clk or negedge rst) begin
  if(!rst) begin
	valid <= 'd0;
  end
  else if(cnt == 'd3)begin
	valid <= 'd1;
  end
  else begin
	valid <= 'd0;
  end
end

logic [3:0] dout_r;
always @(posedge clk or negedge rst) begin
  if(!rst) begin
	dout_r <= 'd0;
  end
  else if(cnt == 'd3)begin
	dout_r <= d;
  end
  else begin
	dout_r <= (dout_r <<1);
  end
end

assign valid_in = valid;
assign dout = dout_r[3];

//*************code***********//

endmodule

认真分析时序关系，valid_in在每次cnt==3的时候拉高，d_r在每次cnt为3的时候保存，之后每个时钟左移移位。

dout位d_r的最高位。