题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg q0;

always@(posedge clk or negedge rst) begin
    if (~rst) q0 <= 1'b0;
    else if(data) q0<=~q0;
    else q0<=q0;
end

always@(posedge clk or negedge rst) begin
    if (~rst) q <= 1'b0;
    else if(q0) q<=~q;
    else q<=q;
end



//*************code***********//
endmodule