题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [4:0] current_state;
reg [4:0] next_state;

always @(posedge clk or negedge rst)begin
	if(!rst)begin
		current_state <= 5'b00001;
	end
	else begin
		current_state <= next_state;
	end
end

always @(posedge clk or negedge rst)begin
	if(!rst)begin
		flag <= 1'b0;
	end
	else begin
		if(current_state == 5'b10000)begin
			flag <= 1'b1;
		end
		else begin
			flag <= 1'b0;
		end
	end
end

always @(*)begin
	case(current_state)
	5'b00001:begin
		if(data)begin
			next_state <= 5'b00010;
		end
		else begin
			next_state <= 5'b00001;
		end
	end
	5'b00010:begin
		if(!data)begin
			next_state <= 5'b00100;
		end
		else begin
			next_state <= 5'b00001;
		end
	end
	5'b00100:begin
		if(data)begin
			next_state <= 5'b01000;
		end
		else begin
			next_state <= 5'b00001;
		end
	end
	5'b01000:begin
		if(data)begin
			next_state <= 5'b10000;
		end
		else begin
			next_state <= 5'b00100;
		end
	end
	5'b10000:begin
		if(data)begin
			next_state <= 5'b00010;
		end
		else begin
			next_state <= 5'b00100;
		end
	end
	default:begin
		next_state <= 5'b00001;
	end
	endcase
end

//*************code***********//
endmodule