题解 | #同步FIFO#

`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);

reg [3:0] write_add;
reg [3:0] read_add;
reg [4:0] count;


always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		write_add <= 4'b0000;
	end
	else begin
		if(winc)begin
			write_add <= write_add + 1;
		end
		else begin
			write_add <= write_add;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		read_add <= 4'b0000;
	end
	else begin
		if(rinc)begin
			read_add <= read_add + 1;
		end
		else begin
			read_add <= read_add;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		count <= 5'b00000;
	end
	else begin
		if(winc)begin
			count <= count + 1;
		end
		else if(rinc)begin
			count <= count - 1;
		end
		else begin
			count <= count;
		end
	end
end

reg wfull_reg;
always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		wfull <= 1'b0;
		wfull <= 1'b0;
	end
	else begin
		if(count == 5'b10000)begin
			wfull <= 1'b1;
		end
		else begin
			wfull <= 1'b0;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		rempty <= 1'b0;
	end
	else begin
		if(count == 5'b00000)begin
			rempty <= 1'b1;
		end
		else begin
			rempty <= 1'b0;
		end
	end
end

dual_port_RAM u0(
	.wclk(clk),
	.wenc(winc),
	.waddr(write_add),
	.wdata(wdata),
	.rclk(clk),
	.renc(rinc),
	.raddr(read_add),
	.rdata(rdata) 		
);

endmodule