题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
//需要一个计数器和寄存器
reg [2:0] data_cnt;
reg [5:0] data_reg;

always@(posedge clk or negedge rst_n) begin
   if(!rst_n)
       ready_a <= 1'b0;
	else
       ready_a <= 1'b1;
end
//
always@(posedge clk or negedge rst_n) begin
   if(!rst_n) begin
       data_cnt <= 3'd0;
	   data_reg <= 6'd0;
    end
	else if(ready_a && valid_a) begin
       data_cnt <= (data_cnt ==3'd5) ? 3'd0:(data_cnt+1'b1);
	   data_reg <= {data_a,data_reg[5:1]};
	end
	else begin
	  data_cnt <= data_cnt;
	  data_reg <= data_reg;
	end
end

always@(posedge clk or negedge rst_n) begin
   if(!rst_n) begin
       valid_b <= 1'b0;
	   data_b <= 6'd0;
   end
	else if(ready_a && valid_a &&(data_cnt ==3'd5)) begin
       valid_b <= 1'b1;
	   data_b <= {data_a,data_reg[5:1]};
	end
	else begin
       valid_b <= 1'b0;
	   data_b <= data_b;
	end
end

endmodule