题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
reg [7:0] cnt;
reg flag;
reg [7:0] clock_r;
always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        flag <= 1'b0;
        cnt <= 8'b0;
    end
    else if(!flag) begin
        if(cnt == 8'd2) begin
            flag <= 1'b1;
            cnt <= 8'b0;
        end
        else begin
            cnt <= cnt + 1'b1;
        end
    end
    else if(pass_request) begin
        if(cnt > 8'd14 && cnt < 8'd65) begin
            cnt <= 8'd65;
        end
        else begin
            cnt <= cnt + 1'b1;
        end
    end
    else if(cnt == 8'd74) begin
        cnt <= 8'b0;
    end
    else begin
        cnt <= cnt + 1'b1;
    end
end
always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        red <= 1'b0;
        yellow <= 1'b0;
        green <= 1'b0;
    end
    else begin
        if(cnt < 8'd9 || cnt == 8'd74) begin
            if(flag == 1'b0 && cnt != 8'd2) begin
                red <= 1'b0;
                yellow <= 1'b0;
                green <= 1'b0;
            end
            else begin
                red <= 1'b1;
                yellow <= 1'b0;
                green <= 1'b0;
            end
        end
        else if(cnt >= 8'd9 && cnt < 8'd14) begin
            red <= 1'b0;
            yellow <= 1'b1;
            green <= 1'b0;
        end
        else if(cnt >= 8'd14 && cnt < 8'd74) begin
            red <= 1'b0;
            yellow <= 1'b0;
            green <= 1'b1;
        end
    end
end
always @ (*) begin
    if(cnt <= 8'd9) begin
        clock_r <= 8'd10 - cnt;
    end
    else if(cnt > 8'd9 && cnt <= 8'd14) begin
        clock_r <= 8'd15 - cnt;
    end
    else begin
        clock_r <= 8'd75 - cnt;
    end
end
assign clock = clock_r;
    
endmodule