题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
	reg [3:0] d_reg;
	reg valid_in_reg;
	reg [1:0] cnt;

	always @(posedge clk or negedge rst) begin
		if(~rst) begin
			cnt <= 2'd3;
		end
		else if(cnt == 2'd0) begin
			cnt <= 2'd3;
		end
		else begin
			cnt <= cnt - 1'b1;
		end 
	end

	always @(posedge clk or negedge rst) begin
		if(~rst) begin
			d_reg <= 4'h0;
		end
		else if(cnt == 2'd0) begin
			d_reg <= d;
		end 
	end

	always @(posedge clk or negedge rst) begin
		if(~rst) begin
			valid_in_reg <= 1'b0;
		end
		else if(cnt == 2'd0) begin
			valid_in_reg <= 1'b1;
		end 
		else begin
			valid_in_reg <= 1'b0;
		end
	end

	assign dout = d_reg[cnt];
	assign valid_in = valid_in_reg;

//*************code***********//

endmodule

第一次运行报错了，看评论区才知道，复位后要4个周期后输出。。。。把第17行的0改成3就正确了。