题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg flag;
reg [7:0] data_in_r;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		flag <= 0;
		data_in_r <= 0;
		data_out <= 0;
		valid_out <= 0;
	end
	else if(valid_in)begin
		flag <= ~flag;
		case(flag)
			1'b0 : begin data_in_r <= data_in; valid_out <= 0; end
			1'b1 :  begin data_out <= {data_in_r,data_in}; valid_out <= 1; end
		endcase
	end
	else begin
		valid_out <= 0;
	end

end




endmodule