题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);


reg [1:0] cnt_2;
reg [7:0] data_in_r;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt_2 <= 0;
	end
	else if(valid_in)begin
		if(cnt_2 == 2)begin
			cnt_2 <= 0;
		end
		else begin
			cnt_2 <= cnt_2 + 1'b1;
		end
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out <= 0;
		data_out <= 0;
		data_in_r <= 0;
	end
	else if(valid_in)begin
		case(cnt_2)
			2'd0 : begin
				data_in_r <= data_in;
				valid_out <= 0;
			end
			2'd1 : begin
				data_in_r <= data_in;
				data_out <= {data_in_r,data_in[7:4]};
				valid_out <= 1;
			end
			2'd2 : begin
				data_out <= {data_in_r[3:0],data_in};
				valid_out <= 1;
			end
			default : valid_out <= 0;		
		endcase
	end
	else begin
		valid_out <= 0;
	end
end





endmodule