题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg [2:0]cnt;
reg clk1;
reg clk2;
reg clk3;



always@(posedge clk_in or negedge rst)begin
    if(~rst)
    cnt<=0;
    else
    cnt<=cnt+1;
end

always@(posedge clk_in or negedge rst)begin
    if(~rst)
    clk1<=0;
    else 
    clk1<=~clk1;
end

always@(posedge clk_in or negedge rst)begin
    if(~rst)
    clk2<=0;
    else if(cnt==0||cnt==2||cnt==4||cnt==6)
    clk2<=~clk2;
end

always@(posedge clk_in or negedge rst)begin
    if(~rst)
    clk3<=0;
    else if(cnt==0||cnt==4)
    clk3<=~clk3;
end

assign clk_out2=clk1;
assign clk_out4=clk2;
assign clk_out8=clk3;

//*************code***********//
endmodule

计数分配即可，简单的偶数分配，到相应的位置翻转