题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0]cnt;
reg [5:0]temp;

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
	cnt<=0;
	else if (valid_a)
	     if(cnt==5)
	       cnt<=0;
		 else
		 cnt<=cnt+1;
	else
	cnt<=cnt;
end


always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
	temp<=0;
	else if (valid_a)
     case(cnt)
	 0:temp[0]<=data_a;
	 1:temp[1]<=data_a;
	 2:temp[2]<=data_a;
	 3:temp[3]<=data_a;
	 4:temp[4]<=data_a;
	 5:temp[5]<=data_a;
	 default temp<=0;
	 endcase
end

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
	ready_a<=0;
	else
	ready_a<=1;
end

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
	valid_b<=0;
	else if (valid_a)
	     if(cnt==5)
	    valid_b<=1;
	else
	valid_b<=0;
end

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
	data_b<=0;
	else if (valid_a)
	     if(cnt==5)
	    data_b<=temp;
	else
	data_b<=data_b;
end



endmodule

观察时序图，发现在数据无效的时候会保cnt的值不变，且计数到5才会拉高