题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

assign ready_a = (valid_b==1'b1) ? ((ready_b==1'b1) ? 1'b1 : 1'b0) : 1'b1;

localparam ADD1 = 2'd0;
localparam ADD2 = 2'd1;
localparam ADD3 = 2'd2;
localparam OUT  = 2'd3;
reg [1:0] state;

always @( posedge clk or negedge rst_n )
begin
	if( !rst_n )
	begin
		valid_b  <= 1'b0;
		data_out <= 10'd0;
		state    <= ADD1;
	end
	else
	begin
		case( state )
		ADD1:
		begin
			if( valid_a==1'b1 && ready_a==1'b1 )
			begin
				valid_b  <= 1'b0;
				data_out <= data_in;
				state    <= ADD2;
			end
			else
			begin
				valid_b  <= valid_b;
				data_out <= data_out;
				state    <= ADD1;
			end
		end
		ADD2:
		begin
			valid_b <= 1'b0;
			if( valid_a==1'b1 && ready_a==1'b1 )
			begin
				data_out <= data_out + data_in;
				state    <= ADD3;
			end
			else
			begin
				data_out <= data_out;
				state    <= ADD2;
			end
		end
		ADD3:
		begin
			valid_b <= 1'b0;
			if( valid_a==1'b1 && ready_a==1'b1 )
			begin
				data_out <= data_out + data_in;
				state    <= OUT;
			end
			else
			begin
				data_out <= data_out;
				state    <= ADD3;
			end
		end
		OUT :
		begin
			if( valid_a==1'b1 && ready_a==1'b1 )
			begin
				valid_b  <= 1'b1;
				data_out <= data_out + data_in;
				state    <= ADD1;
			end
			else
			begin
				valid_b  <= 1'b0;
				data_out <= data_out;
				state    <= OUT; 
			end
		end
		endcase
	end
end

endmodule