题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg [3:0]cnt;
always@(posedge clk_in or negedge rst)
if(!rst)
    cnt<=0;
else begin
    if(cnt==7)
        cnt<=0; 
    else    
        cnt<=cnt+1;   
end

reg rclk_out2;
reg rclk_out4;
reg rclk_out8;
always@(posedge clk_in or negedge rst)
if(!rst)begin
    rclk_out2<=0;
    rclk_out4<=0;
    rclk_out8<=0;
end
else begin
    case(cnt)
    0:begin
        rclk_out2<=1;
        rclk_out4<=1;
        rclk_out8<=1;
    end
    1:begin
        rclk_out2<=0;
        rclk_out4<=1;
        rclk_out8<=1;
    end
    2:begin
        rclk_out2<=1;
        rclk_out4<=0;
        rclk_out8<=1;
    end
    3:begin
        rclk_out2<=0;
        rclk_out4<=0;
        rclk_out8<=1;
    end
    4:begin
        rclk_out2<=1;
        rclk_out4<=1;
        rclk_out8<=0;
    end
    5:begin
        rclk_out2<=0;
        rclk_out4<=1;
        rclk_out8<=0;
    end
    6:begin
        rclk_out2<=1;
        rclk_out4<=0;
        rclk_out8<=0;
    end
    7:begin
        rclk_out2<=0;
        rclk_out4<=0;
        rclk_out8<=0;
    end
    endcase
end
assign clk_out2=rclk_out2;
assign clk_out4=rclk_out4;
assign clk_out8=rclk_out8;
//*************code***********//
endmodule