题解 | #含有无关项的序列检测#强行两个状态机实现

// https://www.nowcoder.com/practice/cba67d06d6834a5d9b93e1087b56c8d8?tpId=302
// 描述
// 请编写一个序列检测模块，检测输入信号a是否满足011XXX110序列（长度为9位数据，前三位是011，后三位是110，中间三位不做要求），当信号满足该序列，给出指示信号match。
`timescale 1ns/1ns
module sequence_detect (
    input wire clk,  // 时钟信号
    input wire rst_n, // 异步复位信号，低电平有效
    input wire a,     // 输入串行数据，最高位先输入
    output reg match  // 输出指示信号，当检测到011XXX110序列时为1
);
reg a_r;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		a_r <= 0;
	end else begin
		a_r <= a;
	end
end

// FSM1
localparam  FSM011_S1 = 3'b001;
localparam  FSM011_S2 = 3'b010;
localparam  FSM011_S3 = 3'b100;
reg [2:0] state_011;
reg [2:0] next_state_011;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		state_011 <= FSM011_S1;
	end else begin
		state_011 <= next_state_011;
	end
end

always @(*)begin
	case(state_011)
		FSM011_S1:next_state_011 = a==0? FSM011_S2:FSM011_S1;
		FSM011_S2:next_state_011 = a==1? FSM011_S3:FSM011_S2;
		FSM011_S3:next_state_011 = a==1? FSM011_S1:FSM011_S2;
		default:next_state_011 = FSM011_S1;
	endcase
end
reg match1;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		match1 <= 0;
	end else if(state_011 == FSM011_S3 && a == 1) begin
		match1 <= 1;
	end else begin
		match1 <= 0;
	end
end

//FSM2
localparam  FSM110_S1 = 3'b001;
localparam  FSM110_S2 = 3'b010;
localparam  FSM110_S3 = 3'b100;
reg [2:0] state_110;
reg [2:0] next_state_110;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		state_110 <= FSM110_S1;
	end else begin
		state_110 <= next_state_110;
	end
end

always @(*)begin
	case(state_110)
		FSM110_S1:next_state_110 = a==1? FSM110_S2:FSM110_S1;
		FSM110_S2:next_state_110 = a==1? FSM110_S3:FSM110_S1;
		FSM110_S3:next_state_110 = a==0? FSM110_S1:FSM110_S3;
		default:next_state_110 = FSM110_S1;
	endcase
end
reg match2;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		match2 <= 0;
	end else if(state_110 == FSM110_S3 && a == 0) begin
		match2 <= 1;
	end else begin
		match2 <= 0;
	end
end


reg match1_r1,match1_r2,match1_r3,match1_r4,match1_r5,match1_r6;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		{match1_r1,match1_r2,match1_r3,match1_r4,match1_r5,match1_r6} <= 6'd0;
	end else begin
		{match1_r1,match1_r2,match1_r3,match1_r4,match1_r5,match1_r6} <= {match1,match1_r1,match1_r2,match1_r3,match1_r4,match1_r5};
	end
end
reg match_r;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		match <= 0;
	end else begin
		match <= match1_r6 & match2;
	end
end

// // shift
// reg[8:0] a_shift_reg;
// always @ (posedge clk or negedge rst_n) begin
// 	if(!rst_n)begin
// 		a_shift_reg <= 0;
// 	end else begin
// 		a_shift_reg <= {a_shift_reg[7:0],a};
// 	end
// end

// always @ (posedge clk or negedge rst_n) begin
// 	if(!rst_n)begin
// 		match <= 0;
// 	end else if({a_shift_reg[8:6],a_shift_reg[2:0]}==6'b011110) begin
// 		match <= 1;
// 	end else begin
// 		match <= 0;
// 	end
// end

endmodule

两个状态机分别检测011和110