题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] temp;
always@(*)begin
    if(sel==0)begin
        temp=d;
        validout=0;
        out=0;
    end
end

always@(posedge clk or negedge rst)begin
    if(!rst)begin 
        out<=0;
        validout<=0;
    end
    else begin
        case(sel)
            2'b01:begin
                validout<=1;
                out<=(temp[3:0]+temp[7:4]);
            end
            2'b10:begin
                validout<=1;
                out<=(temp[3:0]+temp[11:8]);
            end
            2'b11:begin
                validout<=1;
                out<=(temp[3:0]+temp[15:12]);
            end
            default:begin

            end

        endcase

    end
end
//*************code***********//
endmodule