题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	parameter idle=0,a=1,b=2,c=3,d=4,e=5,f=6,g=7;
	reg [2:0]state,next;
	reg [2:0]cnt;
	always@(*)
		begin
			case(state)			
				a: next=data?idle:b;
				b: next=data?c:idle;
				c: next=data?d:idle;
				d: next=data?e:idle;
				e: next=data?idle:f;
				f: next=data?idle:g;
				g: next=data?idle:a;
				idle: next=(cnt==5)?a:idle;
			endcase
		end
	always@(posedge clk,negedge rst_n)
		begin
			if(!rst_n)
				state<=a;
			else
				state<=next;
		end
	always@(posedge clk,negedge rst_n)
		begin
			if(!rst_n)
				cnt<=0;
			else if(cnt==5)
				cnt<=cnt;
			else if(next==idle)
				cnt<=cnt+1;
		end
	always@(*)
		begin
			// if(!rst_n)begin
			// 	match<=0;
			// 	not_match<=0;end
			// else 
			// begin
				if(state==g)
					match<=1;					
				else
					match<=0;
				if(state==idle&cnt==5)
					not_match<=1;
				else
					not_match<=0;
			// end
		end
endmodule