题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output  reg     [4:0]   out,
output  wire            validout
);
//*************code***********//

reg     [15:0]  d_reg;
wire    [3:0]   d0,d1,d2,d3;

assign  {d3,d2,d1,d0} = d_reg[15:0];
assign  validout = | sel;

always@(posedge clk or negedge rst)
    if(!rst)
        d_reg <= 16'b0;
    else if(!validout)
        d_reg <= d;
    else
        d_reg <= d_reg;

always@(*)
    if(!rst)
        out <= 5'b0;
    else
        case(sel)
        2'd0    :   out <= 5'b0;
        2'd1    :   out <= d0 + d1;
        2'd2    :   out <= d0 + d2;
        2'd3    :   out <= d0 + d3;
        default :   out <= 5'b0;
        endcase
        
//*************code***********//
endmodule