题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);
	
//为了zero和number同步，引入一个num_reg寄存

	reg [3:0] num_reg;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			num_reg <= 4'b0;
		end
		else if(mode)begin
			if(num_reg == 4'd9)
				num_reg <=  0;
			else
				num_reg<=num_reg+1;
		end 
		else if(!mode)begin
			if(num_reg == 4'd0)
				num_reg <=  4'd9;
			else
				num_reg<=num_reg-1;
		end 
			
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			zero <= 0;
		end
		else
			zero <= num_reg==4'b0000; 
	end

		always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			number <= 0;
		end
		else
			number <= num_reg;
	end


endmodule