题解 | #Johnson Counter#

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
reg shift_en;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)shift_en<=0;
    else if(Q==4'b0001)shift_en<=0;//shift_en低电平为右移1
    else if(Q==4'b1110)shift_en<=1;//shift_en高电平为右移0
end
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        Q<=4'b0000;
    end
    else begin
        if(!shift_en)begin
            Q<={1'b1,Q[3:1]};
        end
        else Q<={1'b0,Q[3:1]};
    end
end
endmodule