题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0]c0;
compare u0(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(b),
	.c(c0)
);

reg [7:0]c1;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		c1<=0;
	end
	else begin
		c1<=c;
	end
end

compare u1(
	.clk(clk),
	.rst_n(rst_n),
	.a(c0),
	.b(c1),
	.c(d)
);

endmodule


module compare(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	output reg[7:0]c
);

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		c<=0;
	end
	else begin
		if(a>b)begin
			c<=b;
		end
		else begin
			c<=a;
		end
	end

end

endmodule