题解 | #五到一选择器#

`timescale 1ns/1ns

module top_module( 
    input [3:0] a, b, c, d, e, 
    input [2:0] sel,
    output reg [3:0] out );
 always@(*)
 begin
    if(sel==0)
        begin
            out=a;
        end
        else if(sel==1)
        begin 
            out=b;
        end
        else if(sel==2)
        begin 
            out=c;
        end
        else if(sel==3)
        begin 
            out=d;
        end
        else if(sel==4)
        begin 
            out=e;
        end
    end

endmodule