题解 | #信号顺序调整#
信号顺序调整
https://www.nowcoder.com/practice/3f6db9ded7ca4de7981c0a826e924563
`timescale 1ns/1ns
module top_module(
input [15:0] in , output [15:0] out
);
wire [3:0] a,b,c,d;
assign in = {a,b,c,d} , out = {d,c,b,a} ;
endmodule
查看6道真题和解析
