题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	
reg [3:0] RAM [7:0];

integer i;
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		for(i=0 ; i<8 ; i=i+1) RAM[i] <= 4'd0;
	else if(write_en)
		RAM[write_addr] <= write_data;
	else
		for(i=0 ; i<8 ; i=i+1) RAM[i] <= RAM[i];
end

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		read_data <= 4'd0;
	else if(read_en)
		read_data <= RAM[read_addr];
	else
		read_data <= read_data;
end

endmodule