题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//

reg [3:0] RAM [127:0];

integer i;
always@(posedge clk or negedge rst)begin
    if(~rst)
        for(i=0 ; i<128 ; i=i+1) RAM[i] <= 4'd0;
    else if(enb)
        RAM[addr] <= w_data;
    else
        for(i=0 ; i<128 ; i=i+1) RAM[i] <= RAM[i];
end

assign r_data = enb ? 4'd0 : RAM[addr];

//*************code***********//
endmodule