题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);


reg 			[5:0]		line;//sequence
always@(*)
	if(!rst_n) begin
		line 	<= 6'd0;
	end
	else begin
		case(cnt)
			3'd0:line[0] = data;
			3'd1:line[1] = data;
			3'd2:line[2] = data;
			3'd3:line[3] = data;
			3'd4:line[4] = data;
			3'd5:line[5] = data;
			default : ;
		endcase
	end

reg 		[2:0] 		cnt;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		cnt <= 3'd0;
	end
	else if(cnt >=5 )
		cnt <= 3'd0;
	else
		cnt <= cnt + 1'b1;
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		match 		<= 1'b0;
		not_match 	<= 1'b0;
	end 
	else if(cnt == 3'd5)begin
			if(line == 6'b001110)begin
					match 		<= 1'b1;
					not_match 	<= 1'b0;
				end
			else begin
				match 		<= 1'b0;
				not_match 	<= 1'b1;
			end
		end
	else
		begin
			match 		<= 1'b0;
			not_match 	<= 1'b0;
		end
end


endmodule


// 直接寄存 是一定不和题目时序要求的