题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns


module odo_div_or
  #(parameter N = 7)
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

    reg [2:0] cnt;
    always@(posedge clk_in or negedge rst)begin
        if(!rst)
            cnt <= 3'd0;
        else
            cnt <= (cnt == 3'd6) ? 3'd0 : cnt + 1'b1;
    end

    wire clk_tmp1 = cnt >= 3'd3;

    reg clk_tmp2;
    always@(negedge clk_in or negedge rst)begin
        if(!rst)
            clk_tmp2 <= 1'b0;
        else
            clk_tmp2 <= clk_tmp1;
    end

    assign clk_out7 = clk_tmp1 & clk_tmp2;

endmodule

思路：