题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//

reg[7:0]clk_count;
reg[7:0]cnt;

always @(posedge clk_in, negedge rst) begin
    if(rst == 0)begin
        clk_count <= 0;
    end
    else begin
        clk_count <= clk_count==M_N-1 ? 0 : clk_count+1; 
    end
end

wire div_class = clk_count < c89 ? 1 : 0;

always @(posedge clk_in, negedge rst) begin
    if(rst == 0)begin
        cnt <= 0;
    end
    else if(div_class)begin
        cnt <= cnt==(div_e-1) ? 0 : cnt+1;
    end
    else begin
        cnt <= cnt==(div_o-1) ? 0 : cnt+1; 
    end
end

reg clk_out_r;
always @(posedge clk_in, negedge rst) begin
    if(rst == 0)begin
        clk_out_r <= 0;
    end
    else if(div_class)begin
        clk_out_r <= (cnt < div_e>>1) ? 1 : 0;
    end
    else begin
        clk_out_r <= (cnt < div_o>>1) ? 1 : 0;
    end
end
assign clk_out = clk_out_r;

endmodule