题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [4:0]out;
reg [15:0]din;
reg validout;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        out<=5'b0;
        validout<=0;
        din<=16'd0;
    end
    else begin
    case(sel)
        0:begin
            out<=5'd0;
            validout<=0;
            din<=d;
        end
        1:begin
            out<=din[3:0]+din[7:4];
            validout<=1;
        end
        2: begin
            out<=din[3:0]+din[11:8];
            validout<=1;
        end
        3: begin
            out<=din[3:0]+din[15:12];
            validout<=1;
        end
    endcase
    end
end

//*************code***********//
endmodule