题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	reg [5:0] sequence;		  
	reg res;  //compare result for data inputed currently!
	reg [2:0] cnt;
	reg in_data, ctrigger;

	initial begin
		match <= 0;
		not_match <= 0;
		in_data <= 0;
		res <= 0;
		cnt[2:0] <= 3'b000;
		sequence[5:0] <= 6'b001110;
		ctrigger <= 0;
	end

	always @(rst_n) begin
		if (rst_n == 0) begin
			match <= 0;
			not_match <= 0;
			in_data <= 0;
			res <= 0;
			cnt[2:0] <= 3'b000;
		end
	end

	always @(posedge clk) begin 
		if (rst_n == 1) begin
			if ( cnt == 3'b110) 
				cnt <= 1;
			else cnt <= cnt + 1'b1;

			in_data  <= data;
		end
	end

	always @(cnt) begin
		if ( (cnt == 1) | ((cnt > 1) && (res == 1))) begin
		    if (in_data == sequence[cnt-1]) res <= 1;
		    else  res <= 0;
	    end
		ctrigger <= ~ctrigger;
	end
		
	always @(ctrigger) begin
		if ((cnt == 6) && (res == 0)) not_match <= 1;
		if ((cnt == 6) && (res == 1)) match <= 1;
	end

	always @(posedge clk) begin
		match <= 0;
		not_match <= 0;
	end
endmodule