VL28 输入序列不连续的序列检测

VL28 输入序列不连续的序列检测 verilog code

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

	reg [7:0] sequence;		  
	reg pre_result, res;
	reg [31:0] cnt;

 	initial begin
		match <= 0;
		sequence[3:0] <= 4'b0;
		pre_result <= 0;
		res <= 0;
		cnt[31:0] <= 32'b0000;
	end

	always @(rst_n) begin
		if (rst_n == 0) begin
			match <= 0;
			sequence[3:0] <= 4'b0;
			pre_result <= 0;
			res <= 0;
			cnt[31:0] <= 32'b0000;
		end
	end

	always @(posedge clk) begin 
		if ((rst_n == 1) && (data_valid == 1)) begin
			cnt <= cnt + 1'b1;
			sequence[3:1] <= sequence[2:0];
			sequence[0]   <= data;
		end
	end

	always @(cnt)
		if ((cnt >= 4) && (sequence[3:0] == 4'b0110)) 
		    match <= 1;

	always @(posedge clk) begin
		match <= 0;
	end
endmodule

注意：序列匹配后输出的match是一个脉冲，一个周期后必须归0！

另，中拉高match的时间与本题的题目要求不符。题目中要求match在序列匹配后的下一个周期拉高。而用例则是在序列匹配的同周期拉高。